The present invention generally relates to a method and apparatus to optimize intra-module layout in a layout data apparatus, and more particularly, to reduce the time required to generate wiring layout data for a semiconductor integrated circuit (IC) in which inter-module power wirings are optimized.
FIG. 1 is a layout diagram of a single chip semiconductor device 50 in an initial design stage. First, a layout data generating apparatus executes floor plan processing for the semiconductor device 50. Specifically, a plurality of (three in FIG. 1) modules 51 to 53 are laid out on the semiconductor device 50. Subsequently, wirings (inter-module power wirings) 50b for supplying power from external power supply terminals 50a of the chip to each of the modules 51 to 53 are laid out.
The layout data generating apparatus then executes the layout of each of the modules 51 to 53. In other words, various types of cells 51a, power supply wiring (intra-module power wirings) 51b to each of the cells 51a, and module power supply terminals Sic are laid out in the module 51.
After completion of the intra-module layout, the layout data generating apparatus optimizes the layout in accordance with the following steps 1 to 3.
1. As shown in FIG. 2, a power network is sampled based on the various types of the cells 51a and the module power wirings 51b laid out in the module 51. The power network comprises a plurality of equivalent resistances R and current sources CS. Specifically, the power wirings 51b are replaced by a plurality of equivalent resistances R having resistance values determined according to a unit resistance value, wiring length, and wiring width. Because each of the cells 51a and transistors dissipates current, the cells 51a are replaced by the current sources CS with current values determined based on the current consumption. Power networks of the modules 52, 53 are also sampled the same as the module 51.
2. After the power network in each of the modules 51 to 53 has been sampled, the inter-module power wirings 50b are replaced by a plurality of the equivalent resistances R. Thus, the power network of the entire semiconductor device 50 is sampled. Subsequently, the sampled power network is analyzed. Through the analysis of the power network, the current density, voltage drop, and voltage value of the inter-module power wirings 50b are calculated using a well known matrix operation.
3. Based on the analysis results, the excess and deficiency of the inter-module power wirings 50b are determined. The wiring width and position of the inter-module power wirings 50b are corrected in accordance with the determined excess and deficiency of the wirings. That is, the entire semiconductor device 50 is optimized. Specifically, it is determined that the power wirings 50b may become discontinuous or disconnected due to electromigration in the wiring where the current density is higher than a standard. In this case, the power wiring 50b is made thicker or the number of power wirings is increased. Further, it is determined where the area of the power wirings 50b is redundant in the wiring part where the current density is lower than the standard. In this case, a portion of the power wirings 50b is made thinner or eliminated. If the voltage values of the module power supply terminals 51c are lower than standard values, it is determined that the transistors in the modules 51 to 53 may not operate. In this case, the wiring portion having a large voltage drop in the power wirings 50b from the power supply terminals 51c is made thicker or reinforcing wirings are added.
The position and shape of each of the modules 51 to 53 may also need to be changed due to changes of the wiring width and position of the inter-module power wiring 50b. In such a case, the above-mentioned floor plan processing needs to be re-executed. However, the layout in each of the modules 51 to 53 has already been executed based on the current floor plan. Accordingly, by re-executing the floor plan processing, the internal portion of each module needs to be laid out again.
A specific example is shown with a semiconductor device 60 of FIG. 3. A module 61 having relatively high power consumption is laid out at the center of the semiconductor 60, and modules 62 to 65 are laid out around its periphery. Inter-module power wirings 66 are arranged among the respective modules 61 to 65. As shown in FIG. 4A, the sizes of the modules 62 and 64 are reduced as shown by dashed lines, and the spaces between the modules 62 and 64 and their adjacent modules are made wider so that the width of the power wiring 66 facing the center module 61 is increased. As shown in FIG. 4B, intra-module power wirings 62a and 64a can be added to the modules 62 and 64. The amount of current applied to the center module 61 is increased by the added intra-module power wirings 62a and 64a. Accordingly, in such a case, the internal portion of the modules 62 and 64 needs to be laid out again.
After the internal portion of each of the modules 62 and 64 has been laid out again, the above-mentioned optimization is carried out again. Repeating such re-layout and optimization in each module prolongs the layout data generation time of the semiconductor device 60 and increases the design cost of the semiconductor device 60.
It is an object of the present invention to provide a method and device for reducing the layout data generation time.
Briefly stated, the present invention provides a method for generating layout data for a semiconductor integrated circuit having a plurality of modules. Each of the modules has a plurality of cells. First, each of the modules are laid out, and power supply wirings to each of the modules are laid out. Next, information about the cell size of the cells of each module is acquired. Then, the cells are temporarily arranged in each module based on the information about the cell size, and out power wirings and power supply terminals for each module are laid out based on the temporary arrangement of the cells of the modules. A power network is sampled in a unit of each module based on the cells in the module, the power wirings, and the power supply terminals. The sampled power network for each module is analyzed, and it is determined whether each module and the power supply wirings need to be laid out again based on the analysis result.
The present invention provides a recording medium having recorded thereon computer readable program code for generating layout data for a semiconductor integrated circuit. The circuit has a plurality of modules having a plurality of cells. The program causes the computer to execute the above method.
The present invention provides a method for generating layout data for a semiconductor integrated circuit having a plurality of modules. Each module includes a plurality of cells. First, each module is laid out, and power supply wirings to each laid out module are laid out. Next, information about the cell size of the cells of each of the modules is acquired. Then, a plurality of cell lines regions in each module are defined based on the cell size information, and the cells are temporarily arranged in each cell line region. Then, power wirings for each cell line in the module, are laid out, and power supply terminals connected to the power wirings are laid out. A power network in a unit of each module is then sampled based on the cells in the module, the power wirings, and the power supply terminals. The sampled power network is analyzed for each module, and it is determined whether each module and each power supply wiring need to be laid out again based on the analysis result.
The present invention provides a recording medium having recorded thereon computer readable program code for generating layout data for a semiconductor integrated circuit. The circuit has a plurality of modules having a plurality of cells. The program causes the computer to execute the above method.
The present invention provides an apparatus for generating layout data for a semiconductor integrated circuit having a plurality of modules. Each of the modules includes cells. The apparatus includes a memory for storing information about the cell size of the cells of each module. A processor is connected to the memory and executes layout processing. The processor operates to: lay out each module; lay out power supply wirings to the plurality of modules; temporarily arrange the cells in each module based on the cell size information; lay out power wirings and power supply terminals in the module based on the temporary arrangement of the cell; sample a power network in a unit of each module based on the cells in the module, the power wirings, and the power supply terminals; analyze the sampled power network for each module; and determine whether each module and the power supply wirings need to be laid out again based on the analysis result.
The present invention provides an apparatus for generating layout data for a semiconductor integrated circuit having a plurality of modules. Each module includes a plurality of cells. The apparatus includes a memory for storing information about the cell size of the cells of each module. A processor is connected to the memory and executes layout processing. The processor operates to: lay out each module; lay out power supply wirings to the plurality of modules; define a plurality of cell line regions in each module based on the cell size information; temporarily arrange the cells in each cell line region; lay out power wirings for each module including first power wirings in parallel with each cell line in the module and laying out power supply terminals connected to the power wirings; sample a power network in a unit of each module based on the cells in the module, the power wirings, and the power supply terminals; analyze the sampled power network for each module; and determine whether each module and corresponding power supply wiring needs to be laid out again based on the analysis result.